Project Detail
MLM Technology
InternMLC Flash R&D
IC Design & Patent Analysis
Since 2001, contributed as an intern and engineer at MLM Technology, focusing on Multi-Level Cell (MLC) Flash memory.
Performed tasks including HSPICE simulations, IC layout design with L-Edit, and patent analysis for MLC Flash techniques.
Developed an IC layout area cell size estimator program using 0.13um specifications.